The present invention relates to a shift register formed by cascading a plurality of bidirectional register units and, more particularly, to a shift register which can quickly perform processing such as inserting and deleting data with respect to a held data string.
In order to orderly organize data in a communication device or the like by rearranging the data in chronological order or address order, some operation is required for a data string. Conventionally, such a function has been implemented by software processing. For example, new data is generally inserted into a data string by a technique of using a program to shift data located behind the insertion location of the new data one by one and inserting the new data into the resultant free space. A large amount of time is therefore required to insert even one data.
In order to solve this problem, the present inventor has proposed a shift register in Japanese Patent Laid-Open No. 2001-126491 (reference 1), which performs data inserting operation (data construction) with respect to a data string very quickly and easily by using a relatively simple hardware arrangement as compared with conventional software processing.
Although the shift register disclosed in reference 1 can quickly and easily insert data into a data string, it requires a long processing time to delete specific data from a held data string. This is because, in order to delete specific data, data recorded on consecutive shift register units on the subsequent-stage of the shift register on which the data to be deleted is recorded must be sequentially read out, and the read data must be repeatedly written in the preceding-stage shift register units.